As semiconductor technologies rapidly develop, transistor integration density in a chip is increasingly high. In this case, reducing power consumption becomes a key challenge in chip design. A key to reduce power consumption is to reduce a supply voltage of a transistor, and a core restriction factor to reduce the supply voltage is a subthreshold swing of the transistor. A steep subthreshold change allows dramatic supply voltage reduction, so that the power consumption of the transistor is dramatically reduced. A TFET (Tunnel Field-Effect Transistor) is a transistor with a steep subthreshold feature. Therefore, the TFET has extremely great development potential in terms of device power consumption reduction.
FIG. 1 shows a schematic structural diagram of a TFET in the prior art. As shown in FIG. 1, the TFET in the prior art includes a heavily doped source region, a drain region, a channel region, a lightly doped pocket layer, a gate oxide layer, and a gate region, and the pocket layer is located between the gate oxide layer and the source region. Under an action of a gate electric field, carriers of the pocket layer are accumulated and finally form a tunnel junction with the source region, and carriers of the source region are tunneled to the pocket layer to form a current. In FIG. 1, 101 represents the source region, 102 represents the channel region, 103 represents the drain region, 104 represents the pocket layer, 105 represents the gate oxide layer, and 106 represents the gate region.
In an implementation process of the present disclosure, the inventor finds that the prior art has the following problems:
In the TFET shown in FIG. 1, the tunnel junction is formed by enlarging the pocket layer, a tunneling current of this structure is in direct proportion to an area of the pocket layer or carrier tunneling efficiency. The tunneling current may be increased by increasing the area of the pocket layer or the carrier tunneling efficiency. However, due to a technical limitation, it is difficult to increase the carrier tunneling efficiency in the TFET in FIG. 1. Therefore, the tunneling current may be increased by increasing only the area of the pocket layer, but a layout area of the TFET is increased when the area of the pocket layer is increased. In this case, TFET integrity density on a chip is reduced.